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There have been some reports regarding the use of stacked structures to obtain high density integrated circuits 18, to control of OTFT device characteristics 19 and to combine inorganic and organic device processes 20 for the fabrication of the integrated circuits. By combining printing methods with this stacked device structure and using an ultrathin substrate, the processing time is short and total device thickness remains very thin. To overcome this limitation, we have devised a structure for forming vertically stacked p-type and n-type OTFT devices.
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Unfortunately, complex processes such as SAM patterning using a plasma treatment 5 are required to form the source and drain electrodes of each of n and p type OTFT devices on the same substrate, which are unsuitable for volume production and prevent the use of organic transistors in practical applications.
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However, these reports used low performance n-type organic semiconductors or vacuum deposited electrodes.Ĭurrently, the optimization of the electrical characteristics of p-type and n-type OTFT devices requires the modification of the electrode surfaces by using a self-assembled monolayer (SAM) 15, oxide layer 16, or polymer layer 17 processes for the different semiconductor materials. Some studies have examined the printing of circuits that use organic semiconductors (p and n type) 10, 11, 12, while others have investigated hybrid configurations using both inorganic and organic semiconductors 13, 14. A complementary (CMOS) logic configuration is suitable for such devices because of its low power consumption and smaller physical layout compared with the unipolar p-MOS or n-MOS circuit configurations.įabrication of OTFT-based circuits using conventional printing technologies is considered a promising approach due to advantages such as low capital investment, efficient utilization of material and low production cost, motivating extensive research on the fabrication of organic CMOS integrated circuits either entirely or in part by using printing methods.
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In particular, ultrathin devices have received significant consideration for use in practical wearable devices and RFID tags that operate wirelessly and should consume low power and have a small circuit footprint. In recent years, there has been great interest in the use of organic thin film transistor (OTFT) device technology in next-generation thin film electronics, due to the performance enhancements enabled by its use in applications such as flexible displays 1, 2, large-area sensors 3, 4, radio frequency identification (RFID) tags 5, 6 and ultrathin electronics 7, 8, 9. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm 2 V −1 sec −1 and threshold voltages of nearly 0 V with low operating voltages. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices.